Pc-concepts SHG2 DP User Manual download pdf (Page 87)

Intel® SHG2 DP Server Board Technical Product Specification General Specifications

Revision 1.0 Intel Order Number C11343-001

Vout

10% Vout

vout rise

vout on

vout_on

Figure 15. Output Voltage Timing

Table 66 shows the timing requirements for the power supply being turned on and off via the

AC input with PSON held low, and the power supply being turned on and off with the PSON

signal after AC input is applied.

Table 66. Turn On/Off Timing

Item Description Min Max Units

sb_on_delay

Delay from AC being applied to 5VSB being

within regulation.

1500

msec

ac_on_delay

Delay from AC being applied to all output

voltages being within regulation.

2500

msec

vout_holdup

Time all output voltages stay within regulation

after loss of AC.

msec

pwok_holdup

Delay from loss of AC to deassertion of

PWOK

msec

pson_on_delay

Delay from PSON

active to output voltages

within regulation limits.

5 400

msec

pson_pwok

Delay from PSON

deactive to PWOK being

deasserted.

msec

pwok_on

Delay from output voltages within regulation

limits to PWOK asserted at turn on.

100 1000

msec

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 96 97

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