Pc-concepts SHG2 DP User Manual download pdf (Page 50)

Error Reporting and Handling Intel® SHG2 DP Server Board Technical Product Specification

Intel Order Number C11343-001 Revision 1.0

first OEM data byte is 0. The BIOS depends upon the BMC to log the watchdog timer reset

event.

6.3.6 Boot Event

The BIOS downloads the system date and time to the BMC during POST and logs a boot event.

This does not indicate an error, and software that parses the event log should treat it as such.

6.3.7 Chip Set Failure

The BIOS detects the chip set (CMIC-LE and CIOB-X2) failure and logs this event. The chip set

error generates an SMI.

6.4 Firmware (BMC)

The BMC implements the logical SEL device as specified in the Intelligent Platform

Management Interface Specification, Version 1.5. The SEL is accessible via all BMC

transports. This allows the SEL information to be accessed while the system is down via out-of-

band interfaces.

6.4.1 System Event Log (SEL) Full

The BIOS shall generate a POST warning message when the SEL is full. This warning will not

inhibit the system from booting.

6.4.2 Timestamp Clock

The BMC maintains a four-byte internal timestamp clock used by the SEL and SDR

subsystems. This clock is incremented once per second, and is read and set using the Get

SEL Time and Set SEL Time commands, respectively. The Get SDR Time command can also

be used to read the timestamp clock.

The BMC has direct access to the system RTC. This allows the BMC to automatically

synchronize the SEL/SDR timestamp clock to the RTC time on BMC startup, and periodically

reads the RTC to maintain synchrony even when software asynchronously changes the value.

In addition to this, the BIOS sends a timestamp to the BMC using Set SEL Time command

during POST.

6.4.3 Fault Resilient Booting

The Sahalee BMC implements FRB) levels 1, 2, and 3. If the default bootstrap processor (BSP)

fails to complete the boot process, FRB attempts to boot using an alternate processor.

•

FRB level 1 is intended to recover from a BIST failure detected during POST. This FRB

recovery is fully handled by BIOS code.

•

FRB level 2 is intended to recover from a watchdog timeout during POST. The

watchdog timer for FRB level 2 is implemented in the Sahalee BMC.

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Pc-concepts SHG2 DP User Manual Page 50