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Intel® SHG2 DP Server Board Technical Product Specification Processor and Chipset
Revision 1.0 Intel Order Number C11343-001
11
2.3.3 CIOB-X2
The Champion I/O Bridge (CIOB-X2) provides an integrated I/O bridge that provides a high-
performance data flow path between the IMB and the 64-bit I/O subsystem. This subsystem
supports 2 peer 64-bit PCI (-X) segments. Having two PCI (-X) interfaces, the CIOB-X2 is able
to provide large and efficient I/O configurations. The CIOB-X2 functions as the bridge between
IMB and the two 64-bit PCI (-X) I/O segments or peers.
•
The IMB interface is capable of supporting 1.6 GB/s of data bandwidth in both the
upstream and downstream direction simultaneously.
•
The internal PCI (-X) arbiter implements the least-recently used algorithm to grant
access to requesting masters.
•
The CIOB-X2 is a 352-pin ball-grid array (BGA) device.
2.3.3.1 64/100MHz I/O Subsystem
The 64/100MHz subsystem supports the following embedded devices and connectors:
•
One PCI-X network interface controller—Intel 82544GC Gigabit Ethernet Controller with
a dedicated RJ-45 connector.
•
Two 184-pin, 3.3 V keyed, 64-bit PCI expansion slot connectors, numbered PCIX-1 and
PCIX-2, supporting 100-MHz 3.3V-compliant PCI-X adapters, and both 66-MHz and 33-
MHz 3.3V-compliant PCI adapters.
2.3.3.2 64/133 MHz I/O Subsystem
The 64/133 MHz subsystem supports the following embedded device and connector:
•
Dual Channel Ultra 160 SCSI Controller—Adaptec 7899 SCSI Controller. Note: When
the 7899 is enabled, the PCI expansion slot connector would only be capable of running
at 66 MHz PCI mode.
•
One 184-pin, 3.3 V keyed, 64-bit PCI expansion slot connector, numbered PCIX-6
(64/133), supporting 133-MHz 3.3V PCI-X-compliant PCI-X adapters, and MROMB
SCSI adapters.
2.4 CSB5 South Bridge
CSB5 is a multi-function PCI device, housed in a 256-pin BGA device, providing a PCI-to-LPC
bridge, PCI IDE interface, PCI USB controller, and power management controller. Each
function within the CSB5 has its own set of configuration registers. Once configured, each
appears to the system as a distinct hardware controller sharing the same PCI bus interface.
In the SHG2 server board implementation, the CSB5’s primary role is to provide the gateway to
all PC-compatible I/O devices and features. The SHG2 uses the following CSB5 features:
•
PCI bus interface
•
LPC bus interface
•
IDE interface, with dual channel Ultra DMA 100 capability
- SHG2 DP Server Board 1
- Revision History 2
- Disclaimers 2
- Table of Contents 3
- List of Figures 8
- List of Tables 9
- 1. Introduction 13
- 2. Processor and Chipset 18
- 2.2.5 CMIC-LE 20
- 2.3 Memory Subsystem 21
- DIMM 2A, DIMM 2B 2 3, 4 22
- DIMM 3A, DIMM 3B 3 5, 6 22
- Memory DIMM DIMM PAIR Row 22
- DIMM 1A, DIMM 1B 1 1, 2 22
- 2.3.3 CIOB-X2 23
- 2.4 CSB5 South Bridge 23
- 2.4.1 PCI Interface 24
- 2.4.3 USB Interface 24
- 2.4.4 BIOS Flash 24
- 3.1 Overview 30
- 3.3.1 Device IDs (IDSEL) 31
- Baseboard Signals Device 32
- 3.5.1 Device IDs (IDSEL) 33
- 3.5.4 Video Controller 34
- 3.6 Interrupt Routing 35
- 3.6.2 IRQ scan for PCIIRQ 38
- 66/133 MHz 40
- 5.2 System Reset Control 43
- 5.2.2 Hard Reset 44
- 5.2.3 Soft Reset 44
- 6.1 Error Sources and Types 47
- Specification.) 48
- 6.4 Firmware (BMC) 50
- System RAM error 57
- 7.1 Hardware Configuration 60
- 8. Connections 62
- 8.3 SCSI Connectors 64
- 8.4 Floppy Connector 65
- CN31 [Key-H] 65
- 8.5 IDE Connectors 66
- 8.6 Front Panel Interface 67
- CN37 [Key-E] 67
- 8.7 Processor Connector 68
- 8.8.1 ICMB Connector 72
- 8.8.2 Auxiliary I 72
- C* Connector 72
- (FAN1 through FAN8) 73
- 8.9.1 Fan Connector Pin-out 75
- Pin Signal USB Connector 77
- 8.10.3 Serial Ports 78
- 8.10.4 Parallel Port 79
- 8.10.5 Video Port 80
- 8.10.6 Ethernet Connectors 80
- Interface 82
- Definition 82
- 9. General Specifications 84
- 9.3.1 Power Consumption 85
- Conformity) 93
- Conformity 93
- 11.2.4 BSMI (Taiwan) 93
- Appendix A: Glossary 95
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