Pc-concepts SHG2 DP User Manual download pdf (Page 41)

Intel® SHG2 DP Server Board Technical Product Specification Server Management

Revision 1.0 Intel Order Number C11343-001

5. Server Management

The SHG2 server management features are implemented using the Sahalee BMC chip. The

Sahalee BMC is an ASIC packaged in a 156-pin BGA that contains a 32-bit reduced instruction

set computing (RISC) processor core and associated peripherals. Figure 7 illustrates the SHG2

server management architecture. A description of the hardware architecture follows the

diagram.

BASEBOARD

PROCESSOR SOCKETS

SMS #1

I/F

System LPC Bus

12V

3.3V

-12V

Power Button

Front Panel NMI Switch

IERR (2)

Thermal Trip (2)

- Chassis ID

- Baseboard ID

- Power State

NMI

Chip set NMIs

Chip set SMI

CPU Voltage (2)

INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB)

Reset Button

Chassis Intrusion

Power Connector

To Power

Distribution

Board

Baseboard

Temp 1

Private Management Busses

RAM

CODE

(updateable)

SMI

Platform

Management

Interrupt

Routing

Non-volatile, read-write storage

SENSOR

DATA

RECORDS

SYSTEM

EVENT

LOG

FRU INFO

& CONFIG

DEFAULTS

SMM-

BIOS

I/F

COM 2

COMM MUX

BBD COM2

CPU 'Core' Temp (2)

EMP

DIMM SPD (6)

Speaker

Power LED

Fault Status LED

FANs (6)

Sleep Button

Network Activity LEDs

PCI PME

BASEBOARD

MANAGEMENT

CONTROLLER

(BMC)

System I/F

PORTS

1.5V

3.3V Standby

LVDS-B Term. 1

LVDS-A Term. 2

LVDS-A Term. 1

LVDS-B Term. 2

Drive Activity/Fault LED

System Identify Button

NIC #1

NIC #2

RI (Wake-on-Ring)

Chassis

Intrusion

ISOL

LVDS-A Term. 3

LVDS-B Term. 3

Hot-swap

Backplane

Header

Hot-swap

Backplane

Header

Aux. IPMB

Connector

Chip Set

ICMB

Transceiver

Header

Front Panel Connectors

Logic 2.5V

spkr

SMS #2

I/F

ACPI

System Indentify LED

Figure 7. SHG2 Sahalee BMC Block Diagram

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 96 97

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